|
Please note that this page does not hosts or makes available any of the listed filenames. You
cannot download any of those files from here.
|
| 10 - Files.html |
6.47KB |
| 11 - Standard Logic 1164.html |
57.22KB |
| 12 - Standard Logic Text IO Package.html |
3.74KB |
| 13 - Standard Logic Arithmetic.html |
72.08KB |
| 14 - Numeric Bit.html |
89.50KB |
| 15 - IF Statement.html |
4.92KB |
| 16 - CASE Statement.html |
3.90KB |
| 17 - LOOP Statement.html |
5.85KB |
| 18 - NEXT Statement.html |
2.12KB |
| 19 - EXIT Statement.html |
4.74KB |
| 1 - ModelSim Download.txt |
65B |
| 1 - Notepad Download.txt |
50B |
| 1 - Vivado Download.txt |
44B |
| 1 - Welcome to the Course.mp4 |
10.94MB |
| 1 - Welcome to the Course English.srt |
6.71KB |
| 2_1_Mux.vhd |
669B |
| 20 - Entity Example 1 Digital Logic Circuit.mp4 |
10.48MB |
| 20 - Entity Example 1 Digital Logic Circuit English.srt |
5.42KB |
| 21 - Entity Example 2 Multiplexer.mp4 |
11.47MB |
| 21 - Entity Example 2 Multiplexer English.srt |
5.75KB |
| 22 - Architecture Example 1 Digital Logic Circuit.mp4 |
13.47MB |
| 22 - Architecture Example 1 Digital Logic Circuit English.srt |
6.20KB |
| 23 - Architecture Example 2 Multiplexer.mp4 |
15.02MB |
| 23 - Architecture Example 2 Multiplexer English.srt |
7.48KB |
| 24 - Logic Gate VHDL Implementations.html |
6.29KB |
| 25 - AND Gate VHDL Design.mp4 |
14.65MB |
| 25 - AND Gate VHDL Design English.srt |
9.25KB |
| 26 - OR Gate VHDL Design.mp4 |
8.27MB |
| 26 - OR Gate VHDL Design English.srt |
3.58KB |
| 27 - Half Adder Data Flow Design.mp4 |
12.38MB |
| 27 - Half Adder Data Flow Design English.srt |
5.52KB |
| 28 - Full Adder Dataflow Design.mp4 |
17.35MB |
| 28 - Full Adder Dataflow Design English.srt |
7.49KB |
| 29 - Full Adder Behavioral Design.mp4 |
26.12MB |
| 29 - Full Adder Behavioral Design English.srt |
13.66KB |
| 2 - Background.html |
3.38KB |
| 30 - D FlipFlop Behavioral Design.mp4 |
24.83MB |
| 30 - D FlipFlop Behavioral Design English.srt |
13.23KB |
| 31 - Comparator Behavioral Design.mp4 |
19.27MB |
| 31 - Comparator Behavioral Design English.srt |
10.84KB |
| 32 - Full Adder Structural Design.mp4 |
21.74MB |
| 32 - Full Adder Structural Design English.srt |
10.00KB |
| 33 - SetReset Latch Structural Design.mp4 |
18.10MB |
| 33 - SetReset Latch Structural Design English.srt |
8.77KB |
| 34 - 21 Multiplexer Structural Design.mp4 |
20.12MB |
| 34 - 21 Multiplexer Structural Design English.srt |
10.06KB |
| 35 - Full Adder Test Bench Design.mp4 |
31.63MB |
| 35 - Full Adder Test Bench Design English.srt |
15.43KB |
| 36 - D FlipFlop Test Bench Design.mp4 |
41.84MB |
| 36 - D FlipFlop Test Bench Design English.srt |
18.77KB |
| 37 - AND Gate ModelSim Simulation.mp4 |
11.85MB |
| 37 - AND Gate ModelSim Simulation English.srt |
4.99KB |
| 38 - AND Gate Vivado Simulation.mp4 |
19.19MB |
| 38 - AND Gate Vivado Simulation English.srt |
10.97KB |
| 39 - OR Gate ModelSim Simulation.mp4 |
10.85MB |
| 39 - OR Gate ModelSim Simulation English.srt |
4.79KB |
| 3 - VHDL Usage Example 1 Circuit Simulation.mp4 |
9.13MB |
| 3 - VHDL Usage Example 1 Circuit Simulation English.srt |
3.57KB |
| 40 - OR Gate Vivado Simulation.mp4 |
12.82MB |
| 40 - OR Gate Vivado Simulation English.srt |
6.43KB |
| 41 - DFlip Flop ModelSim Simulation.mp4 |
9.52MB |
| 41 - DFlip Flop ModelSim Simulation English.srt |
4.65KB |
| 42 - D FlipFlop Vivado Simulation.mp4 |
19.15MB |
| 42 - D FlipFlop Vivado Simulation English.srt |
10.19KB |
| 43 - Full Adder ModelSim Simulation.mp4 |
9.09MB |
| 43 - Full Adder ModelSim Simulation English.srt |
3.51KB |
| 44 - Full Adder Vivado Simulation.mp4 |
19.15MB |
| 44 - Full Adder Vivado Simulation English.srt |
10.41KB |
| 45 - Priority Encoder VHDL Design.mp4 |
19.62MB |
| 45 - Priority Encoder VHDL Design English.srt |
10.63KB |
| 46 - Priority Encoder Test Bench Design.mp4 |
29.51MB |
| 47 - Priority Encoder Vivado Simulation.mp4 |
21.76MB |
| 47 - Priority Encoder Vivado Simulation English.srt |
9.21KB |
| 48 - Priority Encoder IO Assignments.mp4 |
16.69MB |
| 48 - Priority Encoder IO Assignments English.srt |
7.18KB |
| 49 - Priority Encoder Synthesis and Implementation.mp4 |
7.80MB |
| 49 - Priority Encoder Synthesis and Implementation English.srt |
3.23KB |
| 4 - Objects.html |
1.85KB |
| 50 - Priority Encoder Generating Bitstream.mp4 |
6.20MB |
| 50 - Priority Encoder Generating Bitstream English.srt |
2.05KB |
| 51 - Program and Configure Your FPGA.mp4 |
11.94MB |
| 51 - Program and Configure Your FPGA English.srt |
4.36KB |
| 52 - Test Design on the FPGA.mp4 |
20.42MB |
| 52 - Test Design on the FPGA English.srt |
4.52KB |
| 53 - Appendix A Reading VHDL BNF.html |
3.31KB |
| 54 - Conclusion.mp4 |
4.62MB |
| 54 - Conclusion English.srt |
2.07KB |
| 5 - Signals.html |
4.39KB |
| 6 - Signal Example.mp4 |
12.75MB |
| 6 - Signal Example English.srt |
8.01KB |
| 7 - Variables.html |
3.21KB |
| 8 - VHDL Variable Example.mp4 |
19.90MB |
| 8 - VHDL Variable Example English.srt |
10.46KB |
| 9 - Constants.html |
2.26KB |
| AND_GATE_behav.wdb |
2.92KB |
| And_Gate_Simulation.lpr |
290B |
| And_Gate_Simulation.xpr |
5.85KB |
| AND_GATE_vhdl.prj |
176B |
| AND_GATE.tcl |
460B |
| and_gate.vdb |
1.19KB |
| AND_GATE.vhd |
290B |
| AND_GATE.vhd |
290B |
| AND_GATE.vhd |
290B |
| ARCH_EXAMPLE_1.vhd |
369B |
| ARCH_EXAMPLE_2.vhd |
499B |
| Basys3_Master.xdc |
13.14KB |
| Basys3_Master.xdc |
13.17KB |
| Bonus Resources.txt |
386B |
| Comparator.vhd |
699B |
| Compile_Options.txt |
186B |
| Compile_Options.txt |
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| Compile_Options.txt |
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| Compile_Options.txt |
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| Compile_Options.txt |
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| Compile_Options.txt |
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| compile.bat |
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| compile.bat |
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| compile.bat |
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| compile.bat |
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| compile.bat |
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| compile.log |
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| compile.log |
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| compile.log |
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| compile.log |
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| compile.log |
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| compile.log |
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| DFF_Simulation.lpr |
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| DFF_Simulation.xpr |
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| dff.vdb |
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| Dff.vhd |
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| Dff.vhd |
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| Dff.vhd |
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| elaborate.bat |
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| elaborate.bat |
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| elaborate.bat |
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| elaborate.log |
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| elaborate.log |
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| elaborate.log |
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| elaborate.log |
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| ENTITY_EXAMPLE_1.vhd |
240B |
| ENTITY_EXAMPLE_2.vhd |
306B |
| full_adder_1.vdb |
1.62KB |
| Full_Adder_1.vhd |
426B |
| Full_Adder_1.vhd |
426B |
| Full_Adder_1.vhd |
426B |
| Full_Adder_2.vhd |
1023B |
| Full_Adder_2.vhd |
1023B |
| Full_Adder_3.vhd |
765B |
| Full_Adder_3.vhd |
765B |
| Full_Adder_Simulation.lpr |
290B |
| Full_Adder_Simulation.xpr |
6.32KB |
| gen_run.xml |
6.07KB |
| gen_run.xml |
2.07KB |
| Get Bonus Downloads Here.url |
182B |
| HALF_ADDER.vhd |
338B |
| HALF_ADDER.vhd |
338B |
| HALF_ADDER.vhd |
338B |
| htr.txt |
405B |
| htr.txt |
397B |
| hw.xml |
685B |
| init_design.begin.rst |
176B |
| init_design.end.rst |
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| init_design.pb |
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| ISEWrap.js |
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| ISEWrap.js |
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| ISEWrap.sh |
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| ISEWrap.sh |
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| java_command_handlers.wdf |
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| java_command_handlers.wdf |
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| java_command_handlers.wdf |
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| java_command_handlers.wdf |
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| java_command_handlers.wdf |
1.83KB |
| java_command_handlers.wdf |
41.51KB |
| labtool_webtalk.log |
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| labtool_webtalk.log |
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| NAND_GATE.vhd |
295B |
| NOR_GATE.vhd |
290B |
| NOR_GATE.vhd |
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| opt_design.begin.rst |
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| opt_design.end.rst |
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| opt_design.pb |
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| OR_GATE_behav.wdb |
2.92KB |
| OR_Gate_Simulation.lpr |
290B |
| OR_Gate_Simulation.xpr |
6.39KB |
| OR_GATE_vhdl.prj |
174B |
| OR_GATE.tcl |
460B |
| or_gate.vdb |
1.18KB |
| OR_GATE.vhd |
285B |
| OR_GATE.vhd |
285B |
| OR_GATE.vhd |
285B |
| place_design.begin.rst |
176B |
| place_design.end.rst |
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| place_design.pb |
13.28KB |
| Priority_Encoder_2_238692.backup.vdi |
17.01KB |
| Priority_Encoder_2_clock_utilization_routed.rpt |
7.31KB |
| Priority_Encoder_2_control_sets_placed.rpt |
2.50KB |
| Priority_Encoder_2_drc_opted.rpt |
1.72KB |
| Priority_Encoder_2_drc_routed.pb |
37B |
| Priority_Encoder_2_drc_routed.rpt |
1.80KB |
| Priority_Encoder_2_io_placed.rpt |
60.07KB |
| Priority_Encoder_2_opt.dcp |
115.00KB |
| Priority_Encoder_2_placed.dcp |
117.52KB |
| Priority_Encoder_2_power_routed.rpt |
6.95KB |
| Priority_Encoder_2_power_routed.rpx |
7.42KB |
| Priority_Encoder_2_power_summary_routed.pb |
723B |
| Priority_Encoder_2_propImpl.xdc |
1.93KB |
| Priority_Encoder_2_route_status.pb |
43B |
| Priority_Encoder_2_route_status.rpt |
588B |
| Priority_Encoder_2_routed.dcp |
120.91KB |
| Priority_Encoder_2_timing_summary_routed.rpt |
7.17KB |
| Priority_Encoder_2_timing_summary_routed.rpx |
3.82KB |
| Priority_Encoder_2_utilization_placed.pb |
249B |
| Priority_Encoder_2_utilization_placed.rpt |
7.90KB |
| Priority_Encoder_2_utilization_synth.pb |
249B |
| Priority_Encoder_2_utilization_synth.rpt |
6.78KB |
| Priority_Encoder_2.bit |
2.09MB |
| Priority_Encoder_2.dcp |
7.71KB |
| Priority_Encoder_2.tcl |
1.92KB |
| Priority_Encoder_2.tcl |
1.63KB |
| priority_encoder_2.vdb |
2.63KB |
| Priority_Encoder_2.vdi |
21.70KB |
| Priority_Encoder_2.vds |
17.92KB |
| Priority_Encoder_2.vhd |
794B |
| Priority_Encoder_2.vhd |
794B |
| Priority_Encoder.lpr |
343B |
| Priority_Encoder.xpr |
6.72KB |
| project.wdf |
3.54KB |
| project.wdf |
3.54KB |
| project.wpc |
61B |
| project.wpc |
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| project.wpc |
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| project.wpc |
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| project.wpc |
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| project.wpc |
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| README.txt |
130B |
| README.txt |
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| README.txt |
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| README.txt |
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| README.txt |
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| README.txt |
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| route_design.begin.rst |
176B |
| route_design.end.rst |
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| route_design.pb |
7.96KB |
| rundef.js |
1.37KB |
| rundef.js |
1.30KB |
| runme.bat |
229B |
| runme.bat |
229B |
| runme.log |
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| runme.log |
17.69KB |
| runme.sh |
1.29KB |
| runme.sh |
1.22KB |
| simulate.bat |
279B |
| simulate.bat |
279B |
| simulate.bat |
306B |
| simulate.bat |
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| simulate.bat |
324B |
| simulate.bat |
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| simulate.log |
50B |
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50B |
| simulate.log |
320B |
| simulate.log |
50B |
| simulate.log |
3.43KB |
| simulate.log |
50B |
| SR_LATCH.vhd |
606B |
| synthesis_details.wdf |
100B |
| synthesis.wdf |
5.14KB |
| TempBreakPointFile.txt |
29B |
| TempBreakPointFile.txt |
29B |
| TempBreakPointFile.txt |
29B |
| TempBreakPointFile.txt |
29B |
| TempBreakPointFile.txt |
29B |
| TempBreakPointFile.txt |
29B |
| test_Dff_behav.wdb |
7.63KB |
| test_Dff_vhdl.prj |
258B |
| test_Dff.tcl |
459B |
| test_dff.vdb |
4.98KB |
| test_Dff.vhd |
1.68KB |
| test_Dff.vhd |
1.68KB |
| test_Dff.vhd |
1.68KB |
| test_Full_Adder_1_behav.wdb |
8.37KB |
| test_Full_Adder_1_vhdl.prj |
286B |
| test_Full_Adder_1.tcl |
459B |
| test_full_adder_1.vdb |
6.63KB |
| test_Full_Adder.vhd |
2.31KB |
| test_Full_Adder.vhd |
2.31KB |
| test_Priority_Encoder_2_behav.wdb |
5.61KB |
| test_Priority_Encoder_2_vhdl.prj |
302B |
| test_Priority_Encoder_2.tcl |
460B |
| test_priority_encoder_2.vdb |
4.42KB |
| test_Priority_Encoder_2.vhd |
1.40KB |
| test_Priority_Encoder_2.vhd |
1.40KB |
| usage_statistics_ext_labtool.html |
2.84KB |
| usage_statistics_ext_labtool.html |
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| usage_statistics_ext_labtool.xml |
2.42KB |
| usage_statistics_ext_labtool.xml |
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| usage_statistics_ext_xsim.html |
3.20KB |
| usage_statistics_ext_xsim.html |
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| usage_statistics_ext_xsim.html |
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| usage_statistics_ext_xsim.html |
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| usage_statistics_ext_xsim.html |
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| usage_statistics_ext_xsim.html |
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| usage_statistics_ext_xsim.xml |
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| usage_statistics_ext_xsim.xml |
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| usage_statistics_ext_xsim.xml |
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| usage_statistics_ext_xsim.xml |
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| usage_statistics_ext_xsim.xml |
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| usage_statistics_ext_xsim.xml |
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| usage_statistics_webtalk.html |
18.77KB |
| usage_statistics_webtalk.xml |
25.06KB |
| var_example_behav.wdb |
5.00KB |
| var_example_vhdl.prj |
166B |
| var_example.tcl |
460B |
| var_example.vdb |
2.56KB |
| var_example.vhd |
1.51KB |
| var_example.vhd |
1.51KB |
| VHDL_Variable_Examples.lpr |
290B |
| VHDL_Variable_Examples.xpr |
5.72KB |
| vivado_238692.backup.jou |
898B |
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0B |
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| vrs_config_1.xml |
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| vrs_config_2.xml |
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| vrs_config_3.xml |
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1.07KB |
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107.24KB |
| xsimkernel.log |
324B |
| xsimkernel.log |
324B |
| xsimkernel.log |
340B |
| xsimkernel.log |
322B |
| xsimkernel.log |
354B |
| xsimkernel.log |
330B |
| xvhdl.log |
265B |
| xvhdl.log |
496B |
| xvhdl.log |
556B |
| xvhdl.log |
261B |
| xvhdl.log |
574B |
| xvhdl.log |
261B |
| xvhdl.pb |
400B |
| xvhdl.pb |
750B |
| xvhdl.pb |
810B |
| xvhdl.pb |
396B |
| xvhdl.pb |
828B |
| xvhdl.pb |
396B |