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| 10 - Files.html |
6.47Кб |
| 11 - Standard Logic 1164.html |
57.22Кб |
| 12 - Standard Logic Text IO Package.html |
3.74Кб |
| 13 - Standard Logic Arithmetic.html |
72.08Кб |
| 14 - Numeric Bit.html |
89.50Кб |
| 15 - IF Statement.html |
4.92Кб |
| 16 - CASE Statement.html |
3.90Кб |
| 17 - LOOP Statement.html |
5.85Кб |
| 18 - NEXT Statement.html |
2.12Кб |
| 19 - EXIT Statement.html |
4.74Кб |
| 1 - ModelSim Download.txt |
65б |
| 1 - Notepad Download.txt |
50б |
| 1 - Vivado Download.txt |
44б |
| 1 - Welcome to the Course.mp4 |
10.94Мб |
| 1 - Welcome to the Course English.srt |
6.71Кб |
| 2_1_Mux.vhd |
669б |
| 20 - Entity Example 1 Digital Logic Circuit.mp4 |
10.48Мб |
| 20 - Entity Example 1 Digital Logic Circuit English.srt |
5.42Кб |
| 21 - Entity Example 2 Multiplexer.mp4 |
11.47Мб |
| 21 - Entity Example 2 Multiplexer English.srt |
5.75Кб |
| 22 - Architecture Example 1 Digital Logic Circuit.mp4 |
13.47Мб |
| 22 - Architecture Example 1 Digital Logic Circuit English.srt |
6.20Кб |
| 23 - Architecture Example 2 Multiplexer.mp4 |
15.02Мб |
| 23 - Architecture Example 2 Multiplexer English.srt |
7.48Кб |
| 24 - Logic Gate VHDL Implementations.html |
6.29Кб |
| 25 - AND Gate VHDL Design.mp4 |
14.65Мб |
| 25 - AND Gate VHDL Design English.srt |
9.25Кб |
| 26 - OR Gate VHDL Design.mp4 |
8.27Мб |
| 26 - OR Gate VHDL Design English.srt |
3.58Кб |
| 27 - Half Adder Data Flow Design.mp4 |
12.38Мб |
| 27 - Half Adder Data Flow Design English.srt |
5.52Кб |
| 28 - Full Adder Dataflow Design.mp4 |
17.35Мб |
| 28 - Full Adder Dataflow Design English.srt |
7.49Кб |
| 29 - Full Adder Behavioral Design.mp4 |
26.12Мб |
| 29 - Full Adder Behavioral Design English.srt |
13.66Кб |
| 2 - Background.html |
3.38Кб |
| 30 - D FlipFlop Behavioral Design.mp4 |
24.83Мб |
| 30 - D FlipFlop Behavioral Design English.srt |
13.23Кб |
| 31 - Comparator Behavioral Design.mp4 |
19.27Мб |
| 31 - Comparator Behavioral Design English.srt |
10.84Кб |
| 32 - Full Adder Structural Design.mp4 |
21.74Мб |
| 32 - Full Adder Structural Design English.srt |
10.00Кб |
| 33 - SetReset Latch Structural Design.mp4 |
18.10Мб |
| 33 - SetReset Latch Structural Design English.srt |
8.77Кб |
| 34 - 21 Multiplexer Structural Design.mp4 |
20.12Мб |
| 34 - 21 Multiplexer Structural Design English.srt |
10.06Кб |
| 35 - Full Adder Test Bench Design.mp4 |
31.63Мб |
| 35 - Full Adder Test Bench Design English.srt |
15.43Кб |
| 36 - D FlipFlop Test Bench Design.mp4 |
41.84Мб |
| 36 - D FlipFlop Test Bench Design English.srt |
18.77Кб |
| 37 - AND Gate ModelSim Simulation.mp4 |
11.85Мб |
| 37 - AND Gate ModelSim Simulation English.srt |
4.99Кб |
| 38 - AND Gate Vivado Simulation.mp4 |
19.19Мб |
| 38 - AND Gate Vivado Simulation English.srt |
10.97Кб |
| 39 - OR Gate ModelSim Simulation.mp4 |
10.85Мб |
| 39 - OR Gate ModelSim Simulation English.srt |
4.79Кб |
| 3 - VHDL Usage Example 1 Circuit Simulation.mp4 |
9.13Мб |
| 3 - VHDL Usage Example 1 Circuit Simulation English.srt |
3.57Кб |
| 40 - OR Gate Vivado Simulation.mp4 |
12.82Мб |
| 40 - OR Gate Vivado Simulation English.srt |
6.43Кб |
| 41 - DFlip Flop ModelSim Simulation.mp4 |
9.52Мб |
| 41 - DFlip Flop ModelSim Simulation English.srt |
4.65Кб |
| 42 - D FlipFlop Vivado Simulation.mp4 |
19.15Мб |
| 42 - D FlipFlop Vivado Simulation English.srt |
10.19Кб |
| 43 - Full Adder ModelSim Simulation.mp4 |
9.09Мб |
| 43 - Full Adder ModelSim Simulation English.srt |
3.51Кб |
| 44 - Full Adder Vivado Simulation.mp4 |
19.15Мб |
| 44 - Full Adder Vivado Simulation English.srt |
10.41Кб |
| 45 - Priority Encoder VHDL Design.mp4 |
19.62Мб |
| 45 - Priority Encoder VHDL Design English.srt |
10.63Кб |
| 46 - Priority Encoder Test Bench Design.mp4 |
29.51Мб |
| 47 - Priority Encoder Vivado Simulation.mp4 |
21.76Мб |
| 47 - Priority Encoder Vivado Simulation English.srt |
9.21Кб |
| 48 - Priority Encoder IO Assignments.mp4 |
16.69Мб |
| 48 - Priority Encoder IO Assignments English.srt |
7.18Кб |
| 49 - Priority Encoder Synthesis and Implementation.mp4 |
7.80Мб |
| 49 - Priority Encoder Synthesis and Implementation English.srt |
3.23Кб |
| 4 - Objects.html |
1.85Кб |
| 50 - Priority Encoder Generating Bitstream.mp4 |
6.20Мб |
| 50 - Priority Encoder Generating Bitstream English.srt |
2.05Кб |
| 51 - Program and Configure Your FPGA.mp4 |
11.94Мб |
| 51 - Program and Configure Your FPGA English.srt |
4.36Кб |
| 52 - Test Design on the FPGA.mp4 |
20.42Мб |
| 52 - Test Design on the FPGA English.srt |
4.52Кб |
| 53 - Appendix A Reading VHDL BNF.html |
3.31Кб |
| 54 - Conclusion.mp4 |
4.62Мб |
| 54 - Conclusion English.srt |
2.07Кб |
| 5 - Signals.html |
4.39Кб |
| 6 - Signal Example.mp4 |
12.75Мб |
| 6 - Signal Example English.srt |
8.01Кб |
| 7 - Variables.html |
3.21Кб |
| 8 - VHDL Variable Example.mp4 |
19.90Мб |
| 8 - VHDL Variable Example English.srt |
10.46Кб |
| 9 - Constants.html |
2.26Кб |
| AND_GATE_behav.wdb |
2.92Кб |
| And_Gate_Simulation.lpr |
290б |
| And_Gate_Simulation.xpr |
5.85Кб |
| AND_GATE_vhdl.prj |
176б |
| AND_GATE.tcl |
460б |
| and_gate.vdb |
1.19Кб |
| AND_GATE.vhd |
290б |
| AND_GATE.vhd |
290б |
| AND_GATE.vhd |
290б |
| ARCH_EXAMPLE_1.vhd |
369б |
| ARCH_EXAMPLE_2.vhd |
499б |
| Basys3_Master.xdc |
13.14Кб |
| Basys3_Master.xdc |
13.17Кб |
| Bonus Resources.txt |
386б |
| Comparator.vhd |
699б |
| Compile_Options.txt |
186б |
| Compile_Options.txt |
186б |
| Compile_Options.txt |
204б |
| Compile_Options.txt |
184б |
| Compile_Options.txt |
216б |
| Compile_Options.txt |
192б |
| compile.bat |
317б |
| compile.bat |
317б |
| compile.bat |
335б |
| compile.bat |
315б |
| compile.bat |
347б |
| compile.bat |
323б |
| compile.log |
265б |
| compile.log |
496б |
| compile.log |
556б |
| compile.log |
261б |
| compile.log |
574б |
| compile.log |
261б |
| DFF_Simulation.lpr |
290б |
| DFF_Simulation.xpr |
6.25Кб |
| dff.vdb |
2.44Кб |
| Dff.vhd |
832б |
| Dff.vhd |
832б |
| Dff.vhd |
832б |
| elaborate.bat |
354б |
| elaborate.bat |
354б |
| elaborate.bat |
372б |
| elaborate.bat |
352б |
| elaborate.bat |
384б |
| elaborate.bat |
360б |
| elaborate.log |
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| elaborate.log |
884б |
| elaborate.log |
925б |
| elaborate.log |
692б |
| elaborate.log |
961б |
| elaborate.log |
707б |
| ENTITY_EXAMPLE_1.vhd |
240б |
| ENTITY_EXAMPLE_2.vhd |
306б |
| full_adder_1.vdb |
1.62Кб |
| Full_Adder_1.vhd |
426б |
| Full_Adder_1.vhd |
426б |
| Full_Adder_1.vhd |
426б |
| Full_Adder_2.vhd |
1023б |
| Full_Adder_2.vhd |
1023б |
| Full_Adder_3.vhd |
765б |
| Full_Adder_3.vhd |
765б |
| Full_Adder_Simulation.lpr |
290б |
| Full_Adder_Simulation.xpr |
6.32Кб |
| gen_run.xml |
6.07Кб |
| gen_run.xml |
2.07Кб |
| Get Bonus Downloads Here.url |
182б |
| HALF_ADDER.vhd |
338б |
| HALF_ADDER.vhd |
338б |
| HALF_ADDER.vhd |
338б |
| htr.txt |
405б |
| htr.txt |
397б |
| hw.xml |
685б |
| init_design.begin.rst |
176б |
| init_design.end.rst |
0б |
| init_design.pb |
1.59Кб |
| ISEWrap.js |
7.14Кб |
| ISEWrap.js |
7.14Кб |
| ISEWrap.sh |
1.68Кб |
| ISEWrap.sh |
1.68Кб |
| java_command_handlers.wdf |
766б |
| java_command_handlers.wdf |
9.13Кб |
| java_command_handlers.wdf |
9.05Кб |
| java_command_handlers.wdf |
9.00Кб |
| java_command_handlers.wdf |
1.83Кб |
| java_command_handlers.wdf |
41.51Кб |
| labtool_webtalk.log |
432б |
| labtool_webtalk.log |
430б |
| NAND_GATE.vhd |
295б |
| NOR_GATE.vhd |
290б |
| NOR_GATE.vhd |
290б |
| opt_design.begin.rst |
176б |
| opt_design.end.rst |
0б |
| opt_design.pb |
5.34Кб |
| OR_GATE_behav.wdb |
2.92Кб |
| OR_Gate_Simulation.lpr |
290б |
| OR_Gate_Simulation.xpr |
6.39Кб |
| OR_GATE_vhdl.prj |
174б |
| OR_GATE.tcl |
460б |
| or_gate.vdb |
1.18Кб |
| OR_GATE.vhd |
285б |
| OR_GATE.vhd |
285б |
| OR_GATE.vhd |
285б |
| place_design.begin.rst |
176б |
| place_design.end.rst |
0б |
| place_design.pb |
13.28Кб |
| Priority_Encoder_2_238692.backup.vdi |
17.01Кб |
| Priority_Encoder_2_clock_utilization_routed.rpt |
7.31Кб |
| Priority_Encoder_2_control_sets_placed.rpt |
2.50Кб |
| Priority_Encoder_2_drc_opted.rpt |
1.72Кб |
| Priority_Encoder_2_drc_routed.pb |
37б |
| Priority_Encoder_2_drc_routed.rpt |
1.80Кб |
| Priority_Encoder_2_io_placed.rpt |
60.07Кб |
| Priority_Encoder_2_opt.dcp |
115.00Кб |
| Priority_Encoder_2_placed.dcp |
117.52Кб |
| Priority_Encoder_2_power_routed.rpt |
6.95Кб |
| Priority_Encoder_2_power_routed.rpx |
7.42Кб |
| Priority_Encoder_2_power_summary_routed.pb |
723б |
| Priority_Encoder_2_propImpl.xdc |
1.93Кб |
| Priority_Encoder_2_route_status.pb |
43б |
| Priority_Encoder_2_route_status.rpt |
588б |
| Priority_Encoder_2_routed.dcp |
120.91Кб |
| Priority_Encoder_2_timing_summary_routed.rpt |
7.17Кб |
| Priority_Encoder_2_timing_summary_routed.rpx |
3.82Кб |
| Priority_Encoder_2_utilization_placed.pb |
249б |
| Priority_Encoder_2_utilization_placed.rpt |
7.90Кб |
| Priority_Encoder_2_utilization_synth.pb |
249б |
| Priority_Encoder_2_utilization_synth.rpt |
6.78Кб |
| Priority_Encoder_2.bit |
2.09Мб |
| Priority_Encoder_2.dcp |
7.71Кб |
| Priority_Encoder_2.tcl |
1.92Кб |
| Priority_Encoder_2.tcl |
1.63Кб |
| priority_encoder_2.vdb |
2.63Кб |
| Priority_Encoder_2.vdi |
21.70Кб |
| Priority_Encoder_2.vds |
17.92Кб |
| Priority_Encoder_2.vhd |
794б |
| Priority_Encoder_2.vhd |
794б |
| Priority_Encoder.lpr |
343б |
| Priority_Encoder.xpr |
6.72Кб |
| project.wdf |
3.54Кб |
| project.wdf |
3.54Кб |
| project.wpc |
61б |
| project.wpc |
61б |
| project.wpc |
61б |
| project.wpc |
61б |
| project.wpc |
121б |
| project.wpc |
61б |
| README.txt |
130б |
| README.txt |
130б |
| README.txt |
130б |
| README.txt |
130б |
| README.txt |
130б |
| README.txt |
130б |
| route_design.begin.rst |
176б |
| route_design.end.rst |
0б |
| route_design.pb |
7.96Кб |
| rundef.js |
1.37Кб |
| rundef.js |
1.30Кб |
| runme.bat |
229б |
| runme.bat |
229б |
| runme.log |
21.14Кб |
| runme.log |
17.69Кб |
| runme.sh |
1.29Кб |
| runme.sh |
1.22Кб |
| simulate.bat |
279б |
| simulate.bat |
279б |
| simulate.bat |
306б |
| simulate.bat |
276б |
| simulate.bat |
324б |
| simulate.bat |
288б |
| simulate.log |
50б |
| simulate.log |
50б |
| simulate.log |
320б |
| simulate.log |
50б |
| simulate.log |
3.43Кб |
| simulate.log |
50б |
| SR_LATCH.vhd |
606б |
| synthesis_details.wdf |
100б |
| synthesis.wdf |
5.14Кб |
| TempBreakPointFile.txt |
29б |
| TempBreakPointFile.txt |
29б |
| TempBreakPointFile.txt |
29б |
| TempBreakPointFile.txt |
29б |
| TempBreakPointFile.txt |
29б |
| TempBreakPointFile.txt |
29б |
| test_Dff_behav.wdb |
7.63Кб |
| test_Dff_vhdl.prj |
258б |
| test_Dff.tcl |
459б |
| test_dff.vdb |
4.98Кб |
| test_Dff.vhd |
1.68Кб |
| test_Dff.vhd |
1.68Кб |
| test_Dff.vhd |
1.68Кб |
| test_Full_Adder_1_behav.wdb |
8.37Кб |
| test_Full_Adder_1_vhdl.prj |
286б |
| test_Full_Adder_1.tcl |
459б |
| test_full_adder_1.vdb |
6.63Кб |
| test_Full_Adder.vhd |
2.31Кб |
| test_Full_Adder.vhd |
2.31Кб |
| test_Priority_Encoder_2_behav.wdb |
5.61Кб |
| test_Priority_Encoder_2_vhdl.prj |
302б |
| test_Priority_Encoder_2.tcl |
460б |
| test_priority_encoder_2.vdb |
4.42Кб |
| test_Priority_Encoder_2.vhd |
1.40Кб |
| test_Priority_Encoder_2.vhd |
1.40Кб |
| usage_statistics_ext_labtool.html |
2.84Кб |
| usage_statistics_ext_labtool.html |
2.84Кб |
| usage_statistics_ext_labtool.xml |
2.42Кб |
| usage_statistics_ext_labtool.xml |
2.42Кб |
| usage_statistics_ext_xsim.html |
3.20Кб |
| usage_statistics_ext_xsim.html |
3.20Кб |
| usage_statistics_ext_xsim.html |
3.20Кб |
| usage_statistics_ext_xsim.html |
3.20Кб |
| usage_statistics_ext_xsim.html |
3.20Кб |
| usage_statistics_ext_xsim.html |
3.20Кб |
| usage_statistics_ext_xsim.xml |
2.78Кб |
| usage_statistics_ext_xsim.xml |
2.78Кб |
| usage_statistics_ext_xsim.xml |
2.78Кб |
| usage_statistics_ext_xsim.xml |
2.78Кб |
| usage_statistics_ext_xsim.xml |
2.78Кб |
| usage_statistics_ext_xsim.xml |
2.78Кб |
| usage_statistics_webtalk.html |
18.77Кб |
| usage_statistics_webtalk.xml |
25.06Кб |
| var_example_behav.wdb |
5.00Кб |
| var_example_vhdl.prj |
166б |
| var_example.tcl |
460б |
| var_example.vdb |
2.56Кб |
| var_example.vhd |
1.51Кб |
| var_example.vhd |
1.51Кб |
| VHDL_Variable_Examples.lpr |
290б |
| VHDL_Variable_Examples.xpr |
5.72Кб |
| vivado_238692.backup.jou |
898б |
| Vivado_Implementation.queue.rst |
0б |
| Vivado_Synthesis.queue.rst |
0б |
| vivado.begin.rst |
350б |
| vivado.begin.rst |
175б |
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0б |
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0б |
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898б |
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893б |
| vivado.pb |
149б |
| vivado.pb |
27.93Кб |
| vrs_config_1.xml |
270б |
| vrs_config_2.xml |
284б |
| vrs_config_3.xml |
291б |
| webtalk_10740.backup.jou |
1.07Кб |
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1.15Кб |
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1.12Кб |
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1.12Кб |
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1.19Кб |
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2.11Кб |
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176б |
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0б |
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6.02Кб |
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190б |
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338б |
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380б |
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187б |
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386б |
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183б |
| XNOR_GATE.vhd |
295б |
| XOR_GATE.vhd |
290б |
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59б |
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64б |
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64б |
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64б |
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64б |
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64б |
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64б |
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1.04Кб |
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3.01Кб |
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3.57Кб |
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1.04Кб |
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40б |
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40б |
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40б |
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40б |
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40б |
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122б |
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332б |
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8б |
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8б |
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8б |
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8б |
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8б |
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5.05Кб |
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5.89Кб |
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5.05Кб |
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5.89Кб |
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5.05Кб |
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256б |
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256б |
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256б |
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256б |
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| xsim.xdbg |
136б |
| xsim.xdbg |
408б |
| xsim.xdbg |
680б |
| xsim.xdbg |
136б |
| xsim.xdbg |
600б |
| xsim.xdbg |
584б |
| xsimcrash.log |
1.47Кб |
| xsimcrash.log |
1.39Кб |
| xsimcrash.log |
1.39Кб |
| xsimcrash.log |
1.30Кб |
| xsimcrash.log |
1.12Кб |
| xsimcrash.log |
1.30Кб |
| xsimk.exe |
105.18Кб |
| xsimk.exe |
110.98Кб |
| xsimk.exe |
112.50Кб |
| xsimk.exe |
105.18Кб |
| xsimk.exe |
115.18Кб |
| xsimk.exe |
107.24Кб |
| xsimkernel.log |
324б |
| xsimkernel.log |
324б |
| xsimkernel.log |
340б |
| xsimkernel.log |
322б |
| xsimkernel.log |
354б |
| xsimkernel.log |
330б |
| xvhdl.log |
265б |
| xvhdl.log |
496б |
| xvhdl.log |
556б |
| xvhdl.log |
261б |
| xvhdl.log |
574б |
| xvhdl.log |
261б |
| xvhdl.pb |
400б |
| xvhdl.pb |
750б |
| xvhdl.pb |
810б |
| xvhdl.pb |
396б |
| xvhdl.pb |
828б |
| xvhdl.pb |
396б |